As a verification engineer with a knowledge of subsystems and SoCs you will make valuable contributions to a team tasked with verifying the functional correctness of SoC.
Engineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy.
Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules.
Work with the Emulation/FPGA team in understanding various verification collaterals required for driving stimulus at the board level.
Will collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development.
Senior engineers are also encouraged to support junior members.
Required Skills and Experience :
4-15 years of proven experience in working on IP/Subsystem/Soc Verification
Experienced in one or many of these technologies/ protocols - PCIe, CXL, USB, Ethernet.
Experience in Working on any of cross functional flows like Reset, Ras(Error and Interrupt), Security, low Power for High-speed IO IPs.
Good Skills in System Verilog, shell programming/scripting (e.g. Tcl, Perl, Python etc.)
Experienced in one or more of various verification methodologies – UVM, formal and low power.
Exposure to all stages of verification: requirements collection, creation of test plans, testbench implementation, test cases development, documentation, and support.
Experience with various front-end verification tools - Dynamic simulation tools, Static Simulation tools and Debuggers.
“Nice To Have” Skills and Experience :
Possess knowledge of object-oriented programming concepts
Practical experience of working on Processor based system design
Experience in Server/ Infrastructure SoC
Strong understanding of CPU Architecture/micro-architectures!