Intel DFT Engineer 

United States, Texas, Austin 

622639763

Job Description

Intel is seeking an experienced DFT Engineer to join our team, focusing on the development and integration of Design for Test (DFT) features. This role involves and not limited to:

• Logic Design and RTL Coding: Develop logic design, register transfer level (RTL) coding, and simulation.
• DFT Timing Closure and Test Content: Provide DFT timing closure support and generate test content for SCAN, MBIST, and BSCAN.
• Architecture and Microarchitecture Collaboration: Collaborate in defining architecture and microarchitecture features for blocks, subsystems, and SoCs under DFT design.
• HVM Content Development: Create high-volume manufacturing (HVM) content for rapid bring-up and production on automatic test equipment (ATE).
• RTL and Structural Code Integration: Apply strategies, tools, and methods to write and generate RTL and structural code for DFT integration.
• Optimization: Optimize logic to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals, ensuring design integrity for physical implementation.
• Verification: Review verification plans and drive the verification of DFT designs to meet architecture and microarchitecture specifications. Resolve failing RTL tests to ensure feature correctness.
• Integration and Support: Integrate DFT blocks into functional IP and SoC, supporting SoC customers for high-quality integration.
• Post-Silicon Collaboration: Work with post-silicon and manufacturing teams to verify features on silicon, support debug requirements, and document learnings and improvements.
• Test Coverage: Drive high test coverage through structural and specific IP tests to achieve quality and DPM objectives. Develop HVM content for rapid bring-up and production on ATE.

Minimum Qualifications:

• BS in Electrical Engineering or computer science or related field with 10+ years of experience
• 8+ years of experience in Physical/Structure design
• 5+ years of experience with DFT insertion
• 1+ years of experience with Synopsys or Cadence tools

Preferred Qualifications

• Expertise in Tessent DFT tool
• Primetime expertise, especially in DFT constraints

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits Annual Salary Range for jobs which could be performed in the US $214,730.00-$303,140.00*Salary range dependent on a number of factors including location and experienceThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.