Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, Computer Science, Computer Engineering or related field and 2 years of experience in the job offered or related occupation.
2 years of experience with each of the following skills:
Utilizing Computer Architecture concepts, including pipelined designs, caches, superscalar architecture, and multithreading, to understand graphics processing unit (GPU) architecture specifications.
Experience in ASIC Design, including experience in frontend Logic Design and Verification, understanding data flow of various functional blocks of graphics processing unit (GPU), and developing a functional and performance verification plan.
Using SystemVerilog coding to develop vertically reusable testbench environments.
Experience in developing UVM testbench environments by utilizing knowledge of OOPs concepts like, polymorphism, inheritance, and data encapsulation.
Experience in developing constraint random stimulus for industry standard bus protocols, such as AXI/AHB, running simulations with x-propagation, and performing gate-level and power aware simulations.
Applying UVM, standard methodology for verification, to develop modular, scalable and reusable testbench components.
Experience in industry standard Simulators to compile and run testbench environment, and verify the correctness of GPU IP blocks.