Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience digital design, specializing in power implementation, and developing methodologies and flows for chips with multiple IPs and hierarchical partitions.
Experience using EDA tools like VCLP, Conformal LP, Power-Artist, PT/PTPX, Incisive/VCS.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience in low power digital ASIC design including UPF/CPF, multi-voltage domains, power gating and on chip power management.
Experience in design and analysis of power management IPs with a solid understanding of clock, reset, and power sequencing interactions.
Experience in post-silicon validation and debug.
Experience with gate-level SPICE simulations and statistical SPICE models.
Excellent scripting skills in Tcl, Perl, or Python.