Job Responsibilities
- Custom and compiler memory development including transistor level circuit design, layout, simulation, and quality verification.
- Simulate and analyze the circuit design using transistor level simulators.
- Extract the layout and perform post-layout simulations and verification.
- Review and analyze cell layout for performance, area and reliability.
- Analyze spice simulation data using scripts and spreadsheets.
- Specify and verify various behavioral and physical memory models.
- Document the design specifications, behavioral description, and timing diagrams.
Required Skillset
- Interest in CMOS circuit design with basic understanding of transistor level circuit behavior and device physics.
- Basic familiarity with spice simulators, able to understand and manipulate spice netlists.
- Comfortable with VLSI CAD tools, willing and eager to learn new techniques and tools.
- Can work effectively in engineering compute environment including working knowledge of common unix commands and simple shell, python or perl scripting.
- Good communication, interpersonal, and leadership skills
- Motivated, self-driven and good at multi-tasking
Optional skillset, Areas of Focus and Professional Development
- Proficient in Python, Perl or similar scripting language for automation of everyday tasks and design flows.
- Familiar with Skill programming language
- Familiar with Verilog modeling and simulation
- Basic understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
- Basic understanding of memory behavioral and physical models
- Basic understanding of DFT schemes and chip level integration
- Experience with industry standard analysis flows and tools for functional simulation, formal verification, Static timing, signal integrity, EM/IR and reliability analysis.
- Experience with lab equipment, silicon testing and debug.
Compensation and Benefits
The annual base salary range for this position is 59,000 - $95,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.