Broadcom Digital Design Engineer 

United States, California, San Jose 

593672195

As a Staff Digital Front-End Designer, you will own the design and implementation of complex digital IP and subsystems, focusing on RTL coding, micro-architecture, and design trade-offs. You will collaborate closely with verification engineers and physical design teams to ensure functional correctness, timing closure, and overall design robustness, with a strong focus on critical handling of clock and reset domains crossings.

Technical Leadership and Domain Expertise:

• Lead the design and implementation of advanced digital blocks and subsystems.

• Provide domain expertise in RTL coding, micro-architecture, and PPA trade-offs to optimize performance, power, and area.

RTL Design and Micro-Architecture:

• Develop high-quality RTL designs usingVerilog/SystemVerilog,adhering to best practices and coding standards.

• Define and refine micro-architecture specifications, focusing on efficient and robust design implementations.

Synthesis and Timing Closure:

• Perform synthesis and work with physical design teams to achieve timing closure and optimize multi-clock designs.

• Debug and resolve timing, power, and area issues using tools such as Synopsys Design Compiler and Cadence Genus.

CDC/RDC and Design Quality Assurance:

• Analyze CDC/RDC reports using industry-standard tools (e.g., Spyglass, Questa CDC) to identify and resolve potential issues.

• Apply best practices to ensure robust clock and reset domain crossings while minimizing design risk and complexity.

Verification Collaboration and Formal Methods:

• Collaborate with verification engineers to define test plans, ensure functional coverage, and develop testbench requirements.

• Utilize formal verification tools (e.g., JasperGold, Formality) and static checks to ensure design correctness and robustness.

Optimization and Innovation:

• Continuously explore innovative approaches to optimize designs for PPA, balancing design requirements with project goals.

• Drive iterative improvements based on verification outcomes and analysis feedback.

Documentation and Design Reviews:

• Create and maintain comprehensive design documentation, including micro-architecture specifications, CDC/RDC strategies, and verification plans.

• Participate in cross-functional design reviews to ensure adherence to project goals and high design quality.

Qualifications:

• • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field and 12+ years of experience in digital front-end design, with a focus on complex IP or SoC design or Master’s degree in Electrical Engineering, Computer Engineering, or a related field and 10+ years of experience in digital front-end design, with a focus on complex IP or SoC design.

• Technical Expertise:

  • Strong proficiency in RTL design usingVerilog/SystemVerilog.

  • Expertise in micro-architecture design and PPA trade-offs.

  • Experience in synthesis, STA, and timing closure using tools like Synopsys DC or Cadence Genus.

  • Working knowledge of CDC/RDC analysis and debugging using tools such as Spyglass, Questa CDC, or similar.

• Knowledge Areas:

  • Solid understanding of digital design fundamentals such as pipelining, FSMs, clock domains, and data paths.

  • Familiarity with bus protocols (e.g., AXI, AHB) and memory interfaces.

  • Understanding of low-power design techniques and DFT methodologies is a plus.

• Soft Skills:

  • Strong analytical and problem-solving skills with meticulous attention to detail.

  • Effective communication and collaboration skills to work seamlessly across teams.

  • Ability to manage complex tasks and meet deadlines in a dynamic environment.

Preferred Qualifications:

• Experience with scripting languages (e.g., Python, Perl, TCL) for automation and design tool integration.

• Familiarity with physical design flows and collaboration with back-end design teams.

• Proven track record of successfully handling complex CDC/RDC scenarios in large designs.

Compensation and Benefits

The annual base salary range for this position is $141,000 - $225,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.