Microsoft Senior Fabric Design Engineer 

Taiwan, Taoyuan City 

588362863

Required/minimum qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
• 4+ years of experience in digital logic design for ASIC or FPGA
• 4+ years of logic design flow experience including RTL coding, RTL simulation, synthesis, timing constraints, timing closure

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Additional Preferred:

• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting, etc).
• Demonstrated proficiency in Computer Architecture, Digital Design, CPU/SoC design principles as part of CPU, SoC and/or IP development
• Demonstrated experience and knowledge of design clock crossings and power/UPF.
• Ability to write scripts using Perl, Tcl, Python etc.
• Experience in building and integrating any of the IPs such as protocol bridges, PCIe, cache controllers, memory controllers and DDR, security engines.
• Experience in building functional fabrics using Coherent and Non-Coherent protocols.
• Familiarity with Industry standard interface protocols such as AXI or CHI.
• Familiarity with Synthesis and STA tools.
• Good verbal and written communication skills.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until July 25th, 2025.

• Be part of a design team developing advanced components of the memory sub-system
• Own multiple blocks within a complex, coherent fabric, and bridge IP
• Drive efficiency in integration and automation of highly configurable IPs
• Be responsible for all aspects of the design flow includingmicroarchitecture,RTL coding, Lint, CDC, timing closure, etc
• Collaborate with team members to define interfaces and make optimal design choices
• Work with the verification teams to develop test plans and ensure functional correctness
• Interface with performance modeling, physical design, design for test, and other teams to optimize tradeoffs