What You Can Expect
- Work with design manager to define block micro-architecture and write design specification.
- Implement a specification using RTL coding techniques and best practices
- Work with the physical design teams for synthesis and timing signoff.
- Work with the Verification team on pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis, and full-chip simulation plus debug
What We're Looking For
- BS or MS in Computer or Electrical Engineering
- 5+ years hands-on experience with focus on front-end complex RTL design
- Programming skills in Verilog
- Must be familiar with all stages of theASIC design flow(including specification, architecture,and design implementation)
- Highly motivated and skillful at solving difficult technical problems
- Experience with scripting in Perl/Python/Shell
- Networking, Storage and/or SOC experience is a plus
Expected Base Pay Range (USD)
124,420 - 186,400, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at