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Apple Senior Design Verification Lead United States, Texas, Austin 584220088
07.04.2025
- MS/PhD in Electrical Engineering, Computer Engineering, or a related technical field.
- 12+ years of experience in ASIC/SoC verification, including at least 3 years in a senior leadership role managing teams of engineers.
- Experience with post-silicon validation and debug.
- Familiarity with performance modeling, emulation, or prototyping.
- Hands-on experience with low-power design verification (UPF methodology, clock gating, power intent validation, etc.).
- Understanding of mixed-signal interactions and analog modeling for verification.
- Background in high-speed interfaces (e.g., PCIe, USB, DDR), power-aware verification methodologies, formal verification, and constrained-random testbenches.
- Proven track record of delivering high-performance silicon with first-pass success.
- Deep expertise in SystemVerilog, UVM, and modern verification methodologies.
- Strong debugging and problem-solving skills for complex system-on-chip (SoC) designs.
- Experience leading multi-site teams and cross-functional collaboration with architecture, design, and software groups.
- Experience with coverage-driven verification methodologies and regression-driven verification strategies.
- Excellent communication and leadership skills, with a proven track record of developing high-performing teams and mentoring engineers.
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