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Google Technical Lead Silicon SoC Design 
United States, California, Mountain View 
583730489

03.07.2024
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 10 years of experience with IP development or SoC integration.
  • 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
  • 4 years of experience in people management, developing employees.
  • Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
  • Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
  • Experience with FPGAs and emulation platforms.
  • Experience with high performance and low-power design techniques.
  • Experience with ASIC Verification, DFT, synthesis, STA, or Physical Design.
  • Knowledge in Processor Cores, Buses/Fabric/NoC, Debug/Trace, Interrupts, or Clocks/Reset.