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Microsoft Principal DFT Manager 
Taiwan, Taoyuan City 
583690179

16.10.2025

engineers to help achieve that mission.

Artificial IntelligenceSOCand industry knowledge to envision and implement future technical solutions that will manage andthe Cloud infrastructure.


Qualifications
  • Excellent debug skills for RTL and gate level simulations
  • Experience in DFT scan insertion and or Custom Memory BIST design and verification.
  • Experience withSiemensDFT tools

to meet Microsoft, customer and/or government security screening requirementsfor this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will beto pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Responsibilities
  • Lead DFT strategy and execution across multiple projects, ensuring alignment with overall chip design goals.
  • Define and implement DFT architecture, including scan insertion, boundary scan, MBIST, and JTAG.
  • Collaborate with RTL, physical design, and verification teams to integrate DFT features seamlessly.
  • Manage ATPG and pattern generation, ensuring high fault coverage and test efficiency.
  • Oversee post-silicon bring-up and debug, including test program development and failure analysis.
  • Drive tool and flow development for DFT automation and optimization.
  • Ensure compliance with manufacturing test requirements, including support for ATE platforms.
  • Mentor and guide DFT engineers, fostering technical growth and best practices.
  • Track project milestones and deliverables, reportingstatusand risks to leadership.
  • Evaluate emerging DFT methodologies and tools, recommending improvements to enhance test quality and productivity.