המקום בו המומחים והחברות הטובות ביותר נפגשים
Develop system-level power features to address existing and new productopportunities/requirements.
Understanding and optimizing DL/AI workloads on Data Center platforms.
The prototype features on existing silicon/platforms, lead technical return-on-investment investigations, and design feature bring-up plans for new silicon.
Analyze exciting workload profiles to identify potential opportunities.
Providing input on pitfalls and opportunities during feature proposal reviews.
Lead debug efforts from the HW side to root cause feature sequences bugs, silicon bugs, and sophisticated system-level issues caused by interactions between multiple HW and SW features.
Work closely and proactively with other engineering teams, such as system architects, chip and board designers, software/firmware engineers, HW/SW QA teams, and Applications Engineering teams, to drive next-generation product design, development, debugging, and release.
BS or MS degree in EE/CE or equivalent experience.
Minimum of 8+ years working experience in Energy/Power Optimization, Data Centers, and ASICs.
Experience in working with and optimizing Data Center systems.
Experience with ASIC power-saving features, system-level power-saving features, and experience optimizing products deploying multiple ASICs with shared power constraints.
Deep understanding of firmware/driver structures and their interaction with HW.
Working knowledge of PVT dependencies and binning methodologies.
Strong EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting
Effective in a collaborative environment.
You will also be eligible for equity and .
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