Intel Staff STA Design Automation Engineer 

Malaysia, Penang 

55435531

• To provide technical leadership on the current and next generation FPGA/SOC Timing Modeling and Static Timing Analysis (STA) flow methodology development.
• Defining, implementing and improving the state-of-the-art design solutions (EDA tool, flow and methodology) by sourcing externally or developing the solutions internally.
• Collaborate on HW/SW co-design for next-generation FPGA architectures and timing modeling techniques. Innovate and drive improvements for performance and features for production FPGA devices.
• Develop in-house algorithms, scripts, programs to support design activities, EDA tools technology infrastructure setup, CAD wrappers, GUIs, EDA tools customization and automation program.
• Providing consultation and EDA tools support to the multiple projects in the area of STA, ECO, timing modeling and timing closure.

Requirements:

• BSEE/MSEE or equivalent in with minimum of 10 years experience in IC Design or Design Automation.
• Experience in industry Static Timing Analysis (STA), ECO and Timing Closure flow.
• Thorough knowledge in concepts like Crosstalk, On-Chip-Variation is required.
• Hand on experience in ASIC/SoC design flows and adjacent methodology development/support is required. Experience in advanced process 10nm and below will be plus.
• Programming knowledge in Perl, Python, Tcl/Tk, C-shell or other software languages.
• Proven leadership skills for collaborative cross-functional project.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits