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Tesla Software Engineer AI Inference Codesign United States, California, Palo Alto 552848527
The AI inference codesign team’s goal is to take research models and make them run efficiently on our AI-ASIC to power real-time inference for Autopilot and Optimus programs. This unique role lies at the intersection of AI research, compiler development, kernel optimization, math and HW design. You will work extensively with AI engineers and come up with novel techniques to quantize models, improve precision and explore non-standard alternate architectures. You will be developing optimized micro kernels using a cutting-edge MLIR compiler and solve the performance bottlenecks needed to achieve real-time latency needed for self-driving and humanoid robots. You will work closely with the HW team and bring state-of-the-art HW architecture techniques to our next generation HW SoCs.
- Research and implement state-of-the-art machine learning techniques to achieve high performance on our edge hardware
- Optimize bottlenecks in the inference flow, make precision/performance tradeoff decisions and figure out novel techniques to improve hardware utilization and throughput
- Implement/improve highly performant micro kernels for Tesla’s AI ASIC
- Work with AI teams to design edge friendly neural network architectures
- Collect extensive performance benchmarks (latency, throughput, power) and work with HW teams to shape the next generation of inference hardware, balancing performance with versatility
- Experiment with numerical methods and alternative architectures
- Collaborate with the compiler infrastructure for programmability and performance
- Degree in Engineering, Computer Science or equivalent in experience and evidence of exceptional ability
- Proficiency with Python and C++, including modern C++ (14/17/20)
- Experience with AI networks, such as CNNs, transformers, and diffusion model architectures, and their performance characteristics
- Understanding of GPU, SIMD, multithreading and/or other accelerators with vectorized instructions
- Exposure to computer architecture and chip architecture/micro-architecture
- Specialized experience in one or more of the following machine learning/deep learning domains: Model compression, hardware aware model optimizations, hardware accelerators architecture, GPU/ASIC architecture, machine learning compilers, high performance computing, performance optimizations, numerics and SW/HW co-design
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