Amazon Senior Design Verification Engineer HW Compute Group 

United States, California, Sunnyvale 

548953954

Work hard. Have fun. Make history.In this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for sub-systems and the full chip. You will participate in the design verification and bring-up of the chip and subsystems by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team. You will participate in the lab bring-up of these blocks either in FPGA, emulation, or silicon by potentially writing test scripts, analyzing lab data, proposing experiments, etc.You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering, to architect and implement complex functional block that enable development of world-class hardware devices. In this role, you will:- Design world class hardware and software- Deliver detailed test plans for verification of the full chip or sub-system by working with design engineers and architects
- Create and enhance constrained-random verification environments using SystemVerilog and UVM
- Write tests in C to run out of the CPU
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
- Participate in test plan and coverage reviewsThe ideal candidate should have experience with RTL development environments, fluency in modern hardware description languages and verification methodologies. They should have experience verifying complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. We are looking for a self-driven individual who can work with architects, HW and SW developers and can quickly resolve blocking issues.
Key job responsibilities
- Design Verification of Subsystems such as CPU, NPU, and SOC.
- Drive Verification Methodology using System Verilog / C++ based test benches.

- Bachelor’s degree or higher in EE, CE, or CS
- 10+ years or more of practical semiconductor design verification experience including System Verilog, UVM, assertions and coverage driven verification.
- Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments and system testing
- Experience defining verification methodologies
- Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design
- Experience with writing directed tests
- Experience identifying bugs in architecture, algorithms, functionality and performance with strong overall debug skills
- Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing
- Experience with industry standard tools and scripting languages (Python or Perl) for automation
- Understanding and knowledge of object oriented programming concepts

- PhD in Computer Science, Electrical Engineering, or related field
- Experience with ARM and various DSP ISA
- Experience with CPU block level testing
- Experience debugging system-level issues
- Good programming skills in C/C++ and scripting skills in Python, Tcl, and/or Perl
- 2 years or more of practical experience
- Working experience with high performance industry standard buses like AMBA AXI4
- Experience with formal verification
- Experience with post-silicon validation
- Experience with embedded software
- Experience with transaction level modeling
- Experience with industry standard I/O interfaces
- Knowledge of FPGA and emulation platforms
- Knowledge of SoC architecture
- Excellent verbal and written communication skills