Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
3 years of experience with RTL coding using Verilog/SystemVerilog.
2 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
Experience with low-power design techniques such as clock gating, power gating, and DVFS.
Experience with SOC implementation standards, interfaces (i.e. AXI) and scripting languages (i.e. Tcl, Python or Perl).
Experience in UPF for low-power design, including power intent specification, verification, and implementation.
Experience with formal verification methods and design for testability (DFT) techniques.
Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.