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Apple Chip Level Integration Engineer United States, California, Irvine 52844601
13.06.2024
Description
In this role you will be responsible for top level design development and FE design flows for RTL and Netlist. You will work closely with architecture, verification, CAD, and physical design teams. You will support design teams on different design methodologies, and work towards execution.
Key Qualifications
- 5-10 years experience in chip design
- Experience with FE design tools and methodologies such as: Lint, Synthesis, Logic Equivalence, Clock/reset cross domain verification, FV
- Experience in definition and implementation of low power design (UPF) - advantage
- Familiarity with hierarchical design approach, top-down design
- Good social skills and ability to work collaboratively with other teams
- Ability to develop scripts to facilitate ad-hoc design tasks
- Quick learning of flows and methods
Education & Experience
BSc/ MSc in Electrical Engineering or Computer Engineering.
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