KLA FPGA Design Engineer 

United States, Michigan, Ann Arbor 

521775764

Qualifications

Main job responsibilities in the KLA Design Process include:

• Participate in all phases of FPGA design flow - from concept to wafer inspection tool integration.

• Able to derive FPGA design requirements from system requirements.

• Responsible for RTL design and verification, as well as hardware bring-up.

• Implement logic/control blocks, including custom filters, DSP/image processing blocks, a high-speed image data path, and a processor and memory interface to support real-time processing.

• Optimize FPGA designs for the area, speed, and power to meet system requirements; analyze architectural trade-offs and validate for system sample rate and latency.

• Verify DSP/image processing blocks against Python/MATLAB models and collaborate with systems engineers.

• Run implementation tools, such as Xilinx Vivado and Intel Quartus; perform timing closure for your designs.

• Bring up FPGA design in the lab with necessary lab equipment and complete validation of the design.

• Collaborate with software engineers to integrate the design into wafer Inspection tools.

• Contribute to all phases of hardware development, including creating design documents, reviewing schematics, bringing up new hardware, anddefining/overseeing/performingunit and system tests.

• Validate FPGA design for manufacturing release.

• Experience designing DSP and/or image processing datapath

• Experience in working with FPGAs

• Some experience designing hardware (schematic entry, layout, etc.) is a plus

• Strong programming and scripting skills: MATLAB, Python, C/C++, Perl, Tcl

• Understanding of clock domain crossing (CDC) techniques

• Experience in FPGAs, evaluation boards, and knowledge of FPGA design flow

• Understanding industry-standard interfaces, protocols, and architectures: PCIe, Ethernet, DDR, etc.

• Experience in developing automated, self-checking test benches and/or UVM

• Experience in EDA tools such as simulators (e.g., Questa), and FPGA tools (e.g., Vivado, Quartus)

• Knowledge of timing closure techniques for high-speed design

• Ability to work onsite at least three days per week

Minimum Qualifications

Bachelor’s degree with +5 years’ work experience, OR Master’s degree with +3 years’ work experience, OR PhD with 0 years’ work experience