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Intel GPU Physical Design Engineer 
United States, Texas 
511140441

22.04.2025

Responsibilities

In this position, candidate will be part of a team implementing Integrated and Discrete Graphics blocks on leading edge process technology and EDA tools. The team is responsible for all SoC level physical design and optimization flows ranging from Floorplanning, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN aspects, Layout Verification etc. The ideal candidate will be responsible for development/ implementation and execution of a range of flows on a given design block for Intel graphics projects. The responsibilities may also include defining product requirements such as frequency, operating voltages, etc., coming up with new methodologies/ implementing them and validating them to tackle new challenges presented by the new technologies/ processes/ architectures. The candidate would be required to work closely with the rest of the project team members to resolve issues which arise during the design cycle and take the key learnings into the next product cycle. Good

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship

Minimum Qualifications:

Education Requirements:

  • Bachelor’s in Electrical/Computer Engineering or related field with 4+ years relevant work experience OR

  • Master's in Electrical/Computer Engineering or related field with 3+ years relevant work experience

coursework/experience:

  • Logic Design/VLSI/ASIC Design/Architecture

  • General Knowledge in one or more of ASIC style design flows - floorplanning, synthesis, place/ route, layout verification, static timing analysis

Preferred Qualifications:

  • Preferred knowledge of SoC integration aspects such as floorplan/ timing integration of a variety of RLS blocks

  • Hands-on experience with any of the industry tools in these areas will be an added plus

  • Knowledge and Experience with Unix/ Linux, Perl and TCL in order to implement useable, flexible cshell/ perl/ tcl programs that automate tool/flow methodologies

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