Amazon Sr Physical Design Engineer Annapurna Labs 

United States, California, Cupertino 

51098862

Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.Key job responsibilities
- Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure
- Drive IO/Core block physical implementation through synthesis, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off
- Develop physical design methodologies
- Evaluate 3rd party IP and provide recommendations

- Bachelor's degree in Electrical Engineering or a related field
- Knowledge of UVM and Matlab
- Experience in communication theory, OFDM, MIMO, Digital/Wireless Communication Systems or RF engineering
- Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2 / DVB-C, or related broadband wireless standards

- Master's degree or Ph.D. degree in Electrical Engineering or related field
- Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
- Experience with modern ASIC/FPGA design and verification tools
- Experience with SOC bring-up and post-silicon validation