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Google ASIC RTL Design Engineer ML Accelerators University Graduate United States, California, Sunnyvale 510180083
11.04.2024
Info Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Madison, WI, USA.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
- Academic, educational, internship, or project experience with RTL coding and Verilog/SystemVerilog.
- Experience with a scripting language (e.g., Perl or Python).
Preferred qualifications:
- Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent practical experience.
- Coursework in Digital Design, Computer Architecture, Digital Circuit Design, VLSI Design, Design-for-Test and/or Design Verification.
- Experience with IP development.
- Familiarity with Design Tools related to Verilog simulation, synthesis, static timing analysis, formal verification, power analysis, and/or place and route.
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