Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
2 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based Integrated Circuits (ICs) and chips.
Experience with SystemVerilog (i.e., SystemVerilog Assertions or functional coverage).
Preferred qualifications:
Master's degree or PhD in Electrical Engineering.
6 years of experience in design verification.
Experience with UVM (Universal Verification Methodology).
Experience with industry-standard simulators, revision control systems and regression systems.
Experienced with the full verification life cycle.