Cisco Hardware Modeling Engineer 

United States, California, San Jose 

508794388

The application window is expected to close on February 28, 2025.

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

• You'll joinCisco Silicon One's hardware architecture team, focusing on advanced modeling and simulation using SystemC.
• Contribute to developing complex infrastructure of SystemC behavioral models.
• Your work will enable the infrastructure to support the entire chip design process, enhancing simulation accuracy, performance, and multi-functional collaboration.
• Work closely with ASIC design and verification teams from initial definition to signoff of the chip.
• Work closely with software teams to bring up and enable new features.

• Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related disciplines with 5+ years in ASIC or chip development-related engineering.
• Experience in modeling and simulation, particularly for digital hardware systems.
• Experience in C++ with strong object-oriented programming skills.

• Experience with TLM (Transaction-Level Modeling) and other modeling standards.
• Familiarity with digital design and HDLs such as Verilog or VHDL.
• Strong technical communication and documentation skills.
• Collaborative approach, with meticulous attention to detail and problem-solving abilities.
• Familiarity with networking protocols
• Familiarity with design verification concepts and methodologies
• Experience in scripting languages, such as Python or Perl