Intel Emulation Engineer 

India, Karnataka, Bengaluru 

506249022

Job Description:

We are seeking an experienced Emulation Engineer with a strong background in emulation modeling for SoC and IP designs. The ideal candidate will have 2 to 8 years of hands-on experience with industry-leading platforms such as Palladium (XP, Z1 and Z2) and Zebu, along with expertise in ICE, IXCOM build flow and PCIe. This role will involve designing, developing, and validating complex emulation environments to support our advanced chip designs.

Key Responsibilities:

• Emulation Modeling:

Develop, implement, and maintain emulation models for SoC and IP designs using Palladium (XP, Z1, Z2) and Zebu platforms.
Leverage ICE, IXCOM build flow to ensure robust emulation solutions.

• Verification and Debugging:

Debug and analyze issues related to PCIe and other critical interfaces to ensure design integrity.

• Collaboration and Documentation:

Work closely with design, verification, and system teams to define requirements and develop test plans.
Document test procedures, methodologies, and results to facilitate continuous improvement and knowledge sharing.

• Innovation and Process Improvement:

Required Qualifications:

Bachelor's or Masters degree in Electrical Engineering, Computer Engineering, or a related field.
6+ years of experience in emulation modeling and verification for SoC and IP designs.
Hands on experience with Palladium (XP, Z1 and Z2) and Zebu platforms.
Proficiency in ICE/IXCOM build flow.

Experience with speedbridges Adapters.
Demonstrated expertise in PCIe interface debugging and validation.
Solid understanding of digital design principles and verification methodologies.

Preferred Qualifications (Good-to-Have):

Prototyping Hands-on HAPS System.

Qualifications:

Qualifications:

BE or MTech degree in Electrical Engineering, Computer Engineering, Computer Science. At least 4 to 10 years of experience in the development of IP or SOC verification environments Experience in working with Verilog and System Verilog (UVM - a major advantage). Expertise in vertical and horizontal reuse of verification components Proficiency in SystemVerilog UVM - Great interpersonal skills, and ability to inclusively collaborate with others in group and outside the group Define and develop test env to verify the IP/Sub System functionality. Define Test plans and develop Tests contents. Define Checkers/monitors strategy. Define and Develop Assertions. Define Cover points and analyze functional coverage with analysis. The candidate should have ability to work effectively with both internal and external teams/stakeholders. Should possess strong problemsolving/communicationskills. Should be a very good team player.

1. The only person specialized in Emulation within VTG has resigned, and this area is essential for handling complex IPU debugging tasks.
2. Without immediate replacement, our capacity to address critical debugging issues is diminished, potentially leading to longer resolution times.
3. Bringing in a new expert is essential, not only to fill the immediate gap but also to cultivate and maintain a high level of expertise within the team, ensuring that complex issues can be handled efficiently.
4. The required skillset is highly specialized, and team members without prior experience in this area are unable to manage these tasks.
5. A lack of in-house expertise in Emulation could adversely affect key projects, including PTL/NVL and TTL.
6. A new Emulation expert can provide targeted training and mentorship to existing team members, thereby gradually expanding our internal skillset.

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