Working with end users to understand system use cases to help guide validation
Ensuring a tight loop between hardware qualification and the final application use models
Getting yourself into an exciting emulation world of Hybrid, Virtual Solutions, Industry standard High/Low speed IO IPs based subsystems and integration into SoC
from early architecture and design inputs, to pre-silicon validation, to enable post-silicon validation on emulation platform
Motivated individuals to drive Pre-Silicon story of Emulation across entire SoC teams
The team's early engagement with the design team ensures that quality and debuggability are built into the design
We support architecture, verification, System validation, Performance, Power, DFT teams with insights from performance & power characterization to guide future improvements
We work directly with the verification team to enable a comprehensive pre and post silicon test plan
We write tests, build bare metal drivers for industry standard IO IPs, enable frameworks that will allow us to reuse and scale testing from pre-silicon platforms to many ASIC projects
Required Skills and Experience :
BE or BTech in Electronics Engineering
Candidate must have 8+ years of experience in Pre-Silicon Validation, Emulation/FPGA based platforms
Experience in developing C/C++/SystemC tests in HDL-HVL Co-emulation platforms
Experience in IO bus protocols such as I2C, SPI, USB, and/or PCIe
Experience in debugging tools for systems-on-chip (SoCs) - eg. JTAG, Trace32
“Nice To Have” Skills and Experience :
Knowledge of ASIC design flow, ASIC prototyping flow, and similar
Knowledge of SystemC/C/C++ and UVM/SV verification languages
Experience in these domains: PCIe, Flash, Memory, CPU, GPU, DRAM
Experience with Emulation Tool Chains: Zebu, Veloce, Palladium.