Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
6 years of experience in micro-architecture and coding in one or more of these areas: memory compression, interconnects, coherence, cache, Dynamic Random-Access Memory controller, Physical Layer Device.
Experience with Verilog or System verilog language.
Preferred qualifications:
Experience in High performance design, Multi power domains with Complex clocking. Proven record of multiple SoCs with silicon success.
Experience in micro architecture design and knowledge of system design to develop highly optimized IPs with excellent PPA.
Experience in chip design flow and understanding of cross domain involving Domain Validation / Design for testing / Physical Design.
Experience in various quality checks performed at the front end including Lint, CDC/RDC, Synthesis, Line Echo Cancellation, etc.