In this role, you will be responsible for ensuring bug-free first Test Bring Up for part of the SoC / IP. You are responsible for developing the Test elaboration methodology suitable for the IP, ensuring a scalable and portable environment. You will get to test / using verification environment, including all the respective components such as stimulus, checkers, assertions, code compliance, dashboards. Furthermore, you will develop test plans / Test sequences for all features under your care, code the different test sequence and actively participate to the Test / SoC / IP Bring UP. You will also deeply cooperate with the Digital and Analogue design team and be the Main contributor interacting with the ATE and DFT teams.