Microsoft Senior Logic Design Engineer 

India, Karnataka, Bengaluru 

478495290

the ability to developSilicon Logic Design Efront end logicmicro architecting and designingRTL design, and design quality for our projects. Weare responsible for, CPU-based customIPs, Subsystems,SOC designs that can perform complex and high-performance functions in the most efficient manner. This teaminvolved inprojects within Microsoft developing CPU based SOCs silicon for data cent

• BS/MS in Electrical Engineering or Computer Science/Engineering

• 8+ years logic design experience as a part ofeitherCPU, Cache,Fabric, Digital Power Management, DVFS, Sensors, PCMs,Debug, Peripherals and/or SoC development

• nowledgeof logicdesignflowincluding RTL coding,Synthesis, timing constraints, timing closure.

• expertisein Computer Architecture, Digital Design,IP/SoC design principles as part of SoC and/or IP development.

Additional Preferred Qualification:

• Highly Proficient in Verilog/System Verilog coding constructs.

• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)

• Demonstrated experience and knowledge of clock crossings, and power/UPF in design

• Ability to write scripts using Perl,Tcl, Python etc.

• Familiarity with Industry standard interface protocols is a plus.

• Familiarity withFormal Equivalence Verification and Power Analysisis a plus.

• Good verbal and written communication skills.

to meet Microsoft, customer and/or government security screening requirementsfor this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will beand every two years thereafter.

• Implement the micro-architectural specification in Verilog or System Verilog

• Continue to grow your micro-architectural knowledge and contribute to unit, sub-systemand SOC micro-architecture.

• Development andIntegration of various functional blockRTLinto SoCRTL

• Perform design quality checks such as Timing closure, Lint, CDC, Low Power Intent.

• deliver qualified physical partitionsevaluatingtradeoffs anddeliveringhigh quality design.

• Exercise the functionality of the block by writing basic tests and debug for variousfeatures at IP and SoC levels asdeemednecessary.Automate tasks using scripting for efficiency

• son schedule and with professional integrity

• Challenge the status quo withgrowthmindset.

• Mentor junior team members and summer interns for a growing team