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Intel Physical Design Engineer CPU Core IP United States, Oregon, Hillsboro 472769301
Who You Are
As a core IP Physical Design Engineer your responsibilities include:
Synthesis and Place and Route using industry standard tools for high-speed CPU core design.
Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks, and design closure.
Develop strategies to deliver reproducible design convergence results.
Help to create and refine synthesis flow for the project team.
Develop and recommend better design method practices to enable better synthesis convergence.
The ideal candidate will exhibit behavioral traits that demonstrate: Willingness to work with others in a highly complex decision space.
Skills at developing an implementation plan monitoring key indicators and communicating resource needs and scoping risk to deliver value on schedule.
Excellent verbal and written communication and collaboration skills.
You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Bachelors in Computer Engineering or Electrical Engineering or related technical field with 1+ years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering or related technical field.
Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure.
Experience in PV convergence (including static timing and power analysis).
Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.
Experience in scripting an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby).
Demonstrated success in one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP.
Preferred Qualifications
Industry experience/exposure with CPU Micro-Architecture
Knowledge with Physical design best known practices concerning floor-planning, routing techniques, clock distribution
Knowledge of Static Timing Analysis, Noise analysis, and reliability verification techniques
Knowledge of RTL to GDS methodologies and formal equivalence
Knowledge with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (Genus/Innovus)
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