Intel Physical Design Engineer STA 

United States, California 

471150819

You will be responsible for, but not limited to:

• Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at chip/block level for SoCs.
• Conducts timing rollups, designs for functionality, and develops performance and power optimized clock networks.
• Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently.
• Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on the product plans such as operating conditions and binning.
• Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning.
• Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science with 6+ years of relevant experience listed below OR a Master's degree in in Electrical Engineering, Computer Engineering, Computer Science with 4+ years of relevant experience listed below OR PhD in in Electrical Engineering, Computer Engineering, Computer Science with 2+ years of relevant experience listed below.
• 4+ years of experience in VLSI design, STA sign-off, constraint development.
• 2+ years of experience programming in Perl or Python or Shell scripting, TCL.
• 2+ years of experience supporting post silicon debug.
• 2+ years of experience in EDA tools such as Cadence or Synopsys or Mentor Graphics.

Preferred Qualifications:

• Master's degree in in Electrical Engineering, Computer Engineering, Computer Science with 6+ years of relevant experience OR PhD in in Electrical Engineering, Computer Engineering, Computer Science with 4+ years of relevant experience.
• 6+ years of experience with PrimeTime, Tempus.
• 6+ years of experience defining STA sign-off criteria, methodology, constraints.
• 6+ years of experience leading the execution to drive SoC STA closure for tape-out and supporting silicon debug.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing BenefitsAnnual Salary Range for jobs which could be performed in US, California: $162,041.00-$259,425.00
*Salary range dependent on a number of factors including location and experience