Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
Experience developing and maintaining verification testbenches, test cases, and test environments.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
10 years of experience with Design Verification.
Experience with performance verification of SOCs, pre-silicon analysis, and post silicon correlation.
Experience with building verification methodologies that span simulation, emulation, and FPGA prototypes.
Architectural experience in one or more of the following: Operating Systems, Memory Management, Caches Hierarchies, Coherency, Memory Consistency Models, Memory Ordering, DDR/LPDDR, PCIe, Packet Processors.