Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
Experience verifying digital logic at RTL level using SystemVerilog or C/C++.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation.
Experience with building verification methodologies that span simulation, emulation, and FPGA prototypes.
Experience in one or more of the following: Operating Systems, Memory Management, Caches Hierarchies, Coherency, Memory Consistency Models, Memory Ordering, DDR/LPDDR, PCIe, or Packet Processors.