מציאת משרת הייטק בחברות הטובות ביותר מעולם לא הייתה קלה יותר
Google ASIC RTL Design Engineer United States, California, Sunnyvale 45386153
14.07.2025
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience with Register-Transfer Level (RTL) coding using Verilog/SystemVerilog.
- Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
- 5 years of experience in Application-specific integrated circuit (ASIC) design.
- Experience working on interconnects and network subsystems.
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