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Google ASIC Design Verification Engineer Silicon 
United States, California, Mountain View 
44386128

25.09.2024
Info Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:.
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
  • Experience developing and maintaining verification testbenches, test cases, and test environments.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
  • Experience in different verification techniques and methodologies (e.g., formal, GLS, UPF based Power simulations, UVM and C based testing, etc.) to achieve bug-free Silicon in SoCs.
  • Experience in ARM and RISC-V processor based DV including tool chains and C based testing.