מציאת משרת הייטק בחברות הטובות ביותר מעולם לא הייתה קלה יותר
What you’ll be doing:
Be responsible for the verification of ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using advanced DV methodologies such as UVM.
Building reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
Understanding the design specification and implementation, defining the verification scope, developing test plans, tests, and the verification infrastructure used to verify the correctness of the design.
Collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
What we need to see:
Bachelors or Masters Degree (or equivalent experience) with 8+ years of relevant experience
Experience at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog
Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)
Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies (UVM) and exposure to industry standard verification tools for simulation
Excellent debugging, analytical, and problem solving skills
Great communication and collaboration skills to interact within the team and across functional teams
Ways to stand out from the crowd:
Excellent knowledge of PCIE protocol - Gen3 and above
Good understanding of the system level architecture of PCIE/CXL-based designs
Experience with Perl, Python or similar scripting and/or SW programming languages is highly desireable
You will also be eligible for equity and .
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