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Apple Design Verification Engineer United States, Massachusetts, Waltham 430486507
Yesterday
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage.
- BS degree in technical subject area and a minimum 3 years relevant industry experience or equivalent
- Working knowledge of OOP, SystemVerilog and UVM
- Working knowledge in developing scalable and portable test-benches
- Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations
- Experience with power-aware (UPF) or similar verification methodology
- Knowledge of one of the scripting languages such as Python, Perl, TCL
- Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
- Knowledge of formal verification methodology is a plus but not required
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