Required
- Bachelor of Science in Electrical or Computer Engineering
- 15+ years of experience in hardware design
- 10+ years of experience in Synthesis, Timing constraints, Power Performance Area (PPA) trade-offs
- 10+ yearsexpertisein Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINTclosure.
- Worked with leading-edge technologies5nmand newer
- Experience withleadingdesign teams
- Experiencein developing high speed CMOS designs
- Proficient inSystemVerilog, C/C++, and scripting languages such as Python,Rubyor Perl
Preferred
- Knowledge of the ARM architecture and experience with high-speed IO protocols such as PCI Express or USB
- Strong designknowledge of the industry standardbusinterfaces such as AMBA AXI protocol
- Experienced in Basic floor planning, static timing analysis, closure and working with Physical design team.
- Experience in high-performance/power efficient floating-point design
- Experiencewith chip design quality through design and checklist reviews
- Good communicationand self-motivated that can collaborate with larger teams within Microsoft
- Occasional travel
to meet Microsoft, customer and/or government security screening requirementsfor this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will beto pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.