Microsoft Principal Physical Design Lead 

India, Karnataka, Bengaluru 

974580588

cutting edgelooking for aEnd Implementationto work onIP development as part of theexpanding roadmap of thetechnical environment.

committed to a diverse and inclusive workplace and strongly encourage applicants from allwalks of life. Difference makes us better.

Required

• Bachelor of Science in Electrical or Computer Engineering

• 0+ years of experience in hardware design

• + years of experience in Synthesis, Timing constraints,Front-end design checks andPower Performance Area (PPA) trade-offs

• 8+ years of experience inRTL-to-GDS activities, including PPA optimization, analog integration, and physical signoff activities

• in collateral development including timing and synthesis constraints

• in front-end design checks including LEC, Lint, Formal Equivalence, and CDC/RDC

• in recent synthesis tool capabilities and methods forQoR

• in static timing analysis

• Familiarity with RTL and gate-level power analysis/optimization, UPF, and power-intent verification

• in translating physical design results into feedback for flow or RTL improvement

• inTcl, Perl, Python, shell programming

• in providing technical direction to less-experienced engineers

Preferred

• Occasional travel

You will bekey link betweenwhile you execute individual tasksand providboth RTL-to-validation as well as GDS hardening

For some designs, your responsibility willhandoff to aPursuant tothese tasks, you will beleader in the enablement of quality RTL and collateral file drops to PD,you willbe responsible forimplementing feedback and mitigations in the design constraints and toolchain to ensure best-You will also guide the hardening teamin their execution and sign-offStrong communicationskills will be needed to coordinate with RTL, DFT, CAD andPD hardening

For other designs, your responsibility will be to deliver hardenedIn this, you may alsobe responsible forcustoms macros (memories, PHYs,to understandoffs during this integrationou willbe responsible forsetting schedules and quality definitions for PD drops, while maximizing PPA and ensuringa smoothfor all sign-off activitiesIn this role, you will be expected to coordinate with a diverse set of teams including RTL, DFT, CAD, integration, physical signoff,and program management.

You willbe responsible forflow development, design automation, and correlation exercisesback-end flows. You are expected to work with limited directionattention to detail, and provide technical leadership to other engineers. You will also be expected to be able to provide crisp status of progress, issues, and risks on the program to the management team.