Intel SoC Design Engineer - Block PPA 

United States, Texas 

417037905

Job Description:

As part of Design Enablement's Library and Technology team you will join a highly motivated group of top-notch engineers solving challenging technical problems in physical design pathfinding.

Your responsibilities will include, but are not limited to:

• Perform block PPA with emphasis on synthesis, place, and route on latest internal/external core/graphics/soc designs and target for ambitious power, performance, and area.

• Work with process team to co-define next generation technology node from ground up and push Moore's law to next level.

• Explore standard-cell architectures together with library team and provide guidance to library optimization and choice through block PPA.

• Explore memory options for next technology nodes and provide block PPA impact Co-optimize TFM with EDA tool vendors (primarily Synopsys and Cadence) to boost block PPA and deliver world-class process offering.

• Develop in-house physical design machine learning capability to explore design solution space and push block PPA as well as provide guidance to process technology optimization direction.

• Work intensively with product teams to provide block PPA guidance as well as TFM

• Designdelivery: Bring designs from block PPA and realize in silicon through test-chip and demonstrate world leading silicon.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience.Minimum Qualifications:

• Master's degree in Electrical Engineering, Computer Engineering or related discipline with 2 or more years of professional experience in the areas listed below,
  Or Ph.D. in the same disciplines with 6+ months ofacademic/research/professionalwork in the areas listed below.

• Experience must be in the following:

• SoC/IP physical design using a Cadence and Synopsys design flow.

• Static timing analysis and physical design closure.

Preferred Qualifications:

• Power grid design and IR analysis

• Timing budgets and analysis

• IP block Power, Performance and Area analysis (PPA)

• EDA algorithm customization and optimization

• Scripting language like Python, Perl or TCL

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, California, Santa Clara, US, Texas, Houston

Benefits:

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: