Intel Power Management Micro-Architect 

United States, Texas 

390912169

Job Description:

We are seeking a highly skilled micro-architect with proven expertise and experience in low power management at SoC level. This individual will be responsible for ensuring the successful integration of Power-Management related IPs. Success in this role is both proactive and meeting execution milestones - proactive in working with the IP architects and micro-architects on new features meeting SoC needs; thorough reviews and deep-dives to prove successful integration of PM-related IPs in our SoCs.
As a Micro-Architect, a typical day may include, but is not limited to:

• Becoming an expert and owning the development of a specific area of our SoC infrastructure (IP interconnect Fabrics, Clocks and Resets, Power Management, Boot and Reset Flows, GPIO's, etc.) - in this case, PM
• Leading SoC-level features and strategic initiatives
• Developing micro-architecture for SoC-owned logic blocks
• Building a strong technical understanding of specific IP's and developing expertise in how those IP's fit into SoC and platform level flows
• Providing day-to-day technical guidance and mentoring for SoC integration and validation teams
• Collaborating with pre- and post-silicon validation teams on validation strategies, test plans, coverage matrices, debug, quality reviews, etc.

In addition to the qualifications listed below the ideal candidate will demonstrate the following traits:

• An excellent communicator
• Extremely organized
• A team player who loves to collaborate
• A technical leader who communicates well with great influencing skills
• Someone who meets their commitments
• Motivated
• Self-driven
• Someone who wants to make a difference through technology

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• You must possess a Bachelors in Electrical/Computer Engineering or related field and 17+ years of experience; OR a Masters degree in Electrical/Computer Engineering or related field and 15+ years of experience; OR a PhD in Electrical/Computer Engineering or related field.
• 10+ years of experience in the following:oPower Management flowsoDesigning or validating SoC's, CPU's, or IP blocks experienceoHardware Description Languages such as (System Verilog, Verilog, or VHDL) and Static Timing Analysis.oDesign Quality checks and methodologies experience such as (Clock Domain Crossing (CDC), Lint, etc.).

Preferred Qualifications:

• IP integration and/or SoC-level flows experience, including clocking, boot/reset entry, power management, Design for Test, Design for Debug, Security, IP interconnect fabrics, High speed IO integration, etc.
• Experience in Chipset products or IP's integrated into Chipset experience is a plus.
• Experience with both pre-silicon and post-silicon product development stages

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to

Experienced HireShift 1 (United States of America)US, California, FolsomUS, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

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