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Google Chipset Power Architect Devices Services Silicon 
United States, California, Mountain View 
389612160

29.07.2024
Info Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:.
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • 8 years of experience in power management or low power design/methodology.
  • Experience with low power architecture and power optimization techniques (e.g., multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS, AVS)).
  • Experience with full product delivery cycle (e.g., definition, architecture, design and implementation, testing, productization).

Preferred qualifications:
  • Master's degree or PhD in Electronics or Computer Engineering/Science, with an emphasis on computer architecture, performance and power analysis.
  • Experience with SoC power modeling and analysis.
  • Knowledge of ASIC design flows.
  • Excellent written and verbal communication skills, with the ability to work across cross-functional teams to drive consensus and influence product decisions.