Intel Mixed Signal Logic Design Engineer 

India, Karnataka, Bengaluru 

379402708

Job Description:

Objectives of the position

• Own and deliver the logic design of Mixed Signal IPs.
• Continuously drive turnaround time improvements, robustness of Logic design via Architecture engagement and Tools/Methodology improvements.
• Drive area/power efficiency of IPs and come up with improvements on IP Area/Power metrics.
• Critical Decision making on technical issues.

Qualifications:

The candidate should possess a BS, MS degree with 6+ years of relevant industry experience. Candidate should have worked on IP or SoC RTL logic development using Verilog/System Verilog.Experience in the following areas/skills are desired:

• Logic design using System Verilog
• Low-power design using UPF and clock gating
• Multiple clock domain design
• State machine design
• Simulation and debug experience using VCS/Verdi
• Synthesis and speed path debug
• Git/Perforce/CVS know how
• Strong Perl/Python/TCL scripting skills
• Front-End Design tools like Spyglass or VC Lint, CDC, DFT, VCLP
• Excellent written and verbal communication skills
• DDR PHY and/or Memory Controller Design domain knowledge is a plus
• Experience with DFI/DDR/LPDDR Protocols is a plus
• Basic understanding of analog design to drive an optimal solution between analog and digital designs is a plus
• Familiarity with pre-silicon and post-silicon validation is a plus

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