Microsoft Principal Analog Design Engineer 

India, Karnataka, Bengaluru 

37753110

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

The Microsoft Silicon Team is continuing to revolutionize consumer electronic devices & Cloud Computing.  We are looking for an experiencedanalog design and verification ofnext generation Consumer & Cloud Computing Devices.

The SCIPS Analog group designs high performance mixed signal ASICs in leading edge CMOS technology using custom IC design tools. You will work in a diverse, dynamic environment and interact with other teams to help design and test great products!

The ideal candidate is a self-starter, highly motivated engineer with excellent technical & interpersonal skills, used to working independently or as a key member of a fast-moving design team.

• You should have a BSEE or equivalent, MSEE/PhD preferred.

• You should haveat least10-15years of Analog& Mixed Signal IC circuit design deliveryof medium-large complexity designs.You must have 5 plus years of Lead experience, including day-to-day task coordination and overall delivery responsibilities.

• You have delivered AnalogIP’ssuccessfully in mass productioninFinFETprocesses.

• You have a proventrack recordat each of the following stages in product development:

• Experience in leading high-speed and low-power RX/TX/Clocking designs, High-Speed SerDes or D2D interconnect designs, or large blocks such as PLLs, Power Regulators,Data Converters, etc.

• Design partitioning, power/jitter budgeting and timing analysis.Knowledge of lower power design techniques, calibration, parasitic extraction, EM/IR/ESD & Signal Integrity Design.

• Detailed design and mixed signalsimulatiinsof analog/mixed signal building blocksand one or more of the following subsystems: ADC, DAC, PLL, clocking systems, sampler, RX front-end, TX driver, serializer, de-serializer, voltage regulator, bandgap, bias circuits.

• You have detailed knowledge of EDA tools for Cadence, Mentor, Synopsysfor Analog Design.

• You are a self-starter with the ability to define and adhere to a schedule.

• You have goodinter-personalskills, you are able to interface with a variety of external partners (customers, architects, designers, project managers, etc.) and are able to deliver complete layouts to customers.

Ability to meet Microsoft, customer and/or government security screening requirementsmay befor this role. These requirementsto pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

• The primary responsibility of this position is toleadArchitecture-to-GDS deliveryofcutting edge, high-performance, high-speed, low-powerAnalogIP designs for interconnectivity solutions and fundamental Analog circuit blocks for variousMicrosoftproducts in various process nodes including deepFinFet, following industry best practices.You will technically lead a design teamthat will produce schematics,verify insimulation, and work with mask layout teams to deliver a final IP GDS.
• You will coordinate tasks with junior members of the team, develop plans for AnalogIPexecution, follow processes/methodologies to deliver IP blocks.You are a very hands-oncontributor yourself.
• You will manage on-boarding/offboarding ofadditionalexternal contingent stafftosupplementexistingteam for overflow.
• You are proficient in Analog and Mixed signal IC circuit designs, design validation simulations (preand post-layout), follow checklists/presentation templates, supervise floor-planningandmonitorlayout progress.You will coordinate bench validation of IP in Silicon, and IP characterization on bench and tester.You willestablishflows/methodologies/processes for execution along with peers.
• You willwork along with other members of the team todeliverIP’s, includingproject planning, schedule tracking, report generation.You will follow / augment / put-in-place processes/methodologies in place for high quality execution along with peers.