Cisco STA Engineer 

Armenia, Yerevan 

369655819

• Perform full-chip STA; review and debug issues; provide solutions; and ensure signoff clean results.
• Debug SDC issues and provide feedback to Front-End team
• Perform full-chip timing ECO; deeply explore tool configurations and methodologies; refine and implement efficient strategies to ensure seamless timing ECO execution.
• Generate and provide manual ECOs for timing issues tool can’t handle automatically
• Work closely with block level PD teams to understand each block’s behavior and implementation challenges.

• 5+ years of experience in Static Timing Analysis, including expertise in debugging and developing effective solutions.
• Experience in deep submicron CMOS technologies relevant to process.
• Strong knowledge and experience in CMOS Digital Design Flow.
• Bachelor's or Master's degree in Electrical Engineering or Computer Science or any other relevant field.
• Excellent verbal and written communication skills in English.

• Understanding of the full physical design cycle from RTL to GDSII.
• Hands-on experience in STA and timing ECO.
• Knowledge of scripting languages (Tcl, Python, Shell).

But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)