Intel Memory Tuning Qualification Lead Engineer Discrete Graphics 

Canada, Ontario, Toronto 

36700783

Responsibilities:

Memory sub-system validation engineer's responsibility includes planning, execution, and debug for pre- and post-silicon validation.

Develop and execute test plans for functional and electrical validation (PVT shmoo characterization).

Professional traits:

The candidate possess knowledge of memory subsystem, including SoC memory architecture, memory controller, PHY design and high speed IO interface, DRAM device, and associated calibration/training mechanisms.

Proven ability to drive resolution of critical problems, while under pressure.

Minimum qualifications

• Bachelor's degree in Electrical or Computing engineer or related field
• 8+ years Debug skills to root cause post-production issues and/or customer returns
• 8+ years experience in validation, or verification and/or debug of memory sub-system
• 8+ years Ability to apply knowledge of other high-speed, high-performance memory technologies

Preferred experience:

• 5+ years Experience working with major DRAM memory vendors and validation of DRAM device
• 5+ years Hands-on experience in using industry standard JTAG, I2C, Tester and Lab tools
• 5+ years Programming skills (C/C++, Python) and comfortable working on Linux or Windows platforms