Amazon Serdes PHY Expert Annapurna Labs 

United States, Texas, Austin 

365434950

Key job responsibilities
You will collaborate with architects, design teams, software engineers to deliver the next generation ML chip. In this position, you will have the opportunity to be responsible for IP integration, 2.5D design, bring up, Characterization and validation.Austin, TX, USA

-BS or MS in EE, ECE or CS
-7+ years of experience in Silicon development with -3+ years in SOC/IO/Subsystems
-Deep understanding of Serdes/PCIE at the PHY and controller level including inner workings of PHY component blocks
-Familiar with industry standard protocols such as PCIE
-Experience with test chip characterization and testing compliance
-Experience with post silicon testing include of shmoos including BER, PRBS, Eq settings
-Drive the IP Integration and design of silicon and 2.5D packaging
-Support the physical design team, review clocking and timing constraints
-Drive cross-functional triage effort on complex functional and performance issues
-Take the leadership role in post-silicon bring-up including test plans and execution
-Knowledge of channel electrical and associated tuning parameters, e.g. TX PSET values, RX equalization
-Perform system-level debug and root-cause analysis through bring-up, characterization, validation and production phase
-Experience Working with 3rd party IP vendors
-Strong Firmware development skills within embedded environments