Nvidia Senior DFX Methodology Engineer 

United States, California 

365302096

What you'll be doing:

• As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, IO BIST, memory BIST and scan compression.

• In addition, you will help develop and deploy DFT methodologies for our next generation products

• You will also help mentor junior engineers on test designs and trade-offs including cost and quality.

What we need to see:

• BSEE (or equivalent experience) with 4+, MSEE (or PhD ) with 2+ years of proven experience in DFT or related domains

• Proven knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation

• Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools

• Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs

• Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development

• Strong programming and scripting skills in Perl, Python or Tcl desired

• Exceptional written and oral interpersonal skills with the curiosity to work on rare challenges