Intel Senior Foundry Applications Engineer ASIC Physical Design 

United States, Texas 

360642584

Job Description:

The Aerospace, Defense, Government (ADG)-Senior Foundry Applications Engineer (ASIC Physical Design) provides technical support to Intel Foundry Services customers on our PDKs, Digital reference flows, and digital design signoff methodology. The successful candidate will:

• Collaborate with internal teams across Intel and external stakeholders such as foundry customers' design teams, IP providers, and EDA vendors on issue resolution.
• Create content, application notes and deliver technicaltraining/presentations.
• Drive quality of design kits and documentation through ASIC design reference flow validation and reviewing documentation
• Support and provideTool/Flow/Methodologyon customer issues and challenges for successful customer tape-outs, and to increase customer satisfaction

The ideal candidate will have the following skills in addition to the qualifications listed below:

• Self-driven and results-oriented, capable of effectively working multiple tasks.
• Team player - effective team-work skillset to drive and find solutions for customer design implementation issues/challenges
• Analytical problem-solving skills.
• Effective communication skills, as well as experience in collaboration, listening and providing feedback.

Minimum Qualifications

• US Citizenship required.
• Ability to obtain a US Government Security Clearance.
• Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• 5+ years of experience with advanced CMOS processes (16nm and below).
• 4+ years of experience in ASIC physical design implementation and/or ASIC design signoff (SOC/ASIC).
• 4+ years of experience in scripting languages like Python, Perl, Tcl, and/or shell scripting.

Preferred Qualifications

• Active US Government Security Clearance with a minimum of Secret level.
• Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• Hands-on experience in one or more areas of ASIC Design Implementation and methodology, Full chip Integration, Synthesis, APR, Static Timing Analysis, Layout Verification and Reliability Verification.
• Experience with major EDA tools and flows and tools (Fusion Compiler, PrimeTime, PrimeECO, ICV) and/or Cadence Suite (Innovus, Tempus, TempusECO, Pegasus, Voltus).
• Experience using hierarchical and multi-voltage domain design approach, top-down design, budgeting, timing and physical convergence, Correlation across implementation and Verification Tools and building Quality Assurance (QA) regression.
• Customer facing experience.
• Experience in SOTA Process technology (7nm and below).

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, California, Santa Clara, US, Oregon, Hillsboro
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.