This role is for a Senior Principal DFT Engineer with 15+ years of experience in Design for Test
Experience coding Verilog RTL, TCL and/or Perl
Proficient in Unix/Linux environments
Core DFT skills considered for this position should include some of the following: Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics
Bachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field
“Nice To Have” Skills and Experience :
Familiarity with IEEE 1149, 1500, 1687, 1838
Synthesis & Static Timing Analysis
Familiarity with SoC style architectures including multi-clock domain and low power design practices.
Validated understanding of Siemens DFT tools
Familiarity with Arm IP like the following: Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug
Experience with 2.5D and 3D test
Ability to work both collaboratively on a team and independently
Hard-working and excellent time management skills with an ability to multi-task
An upbeat demeanor to working on exciting projects on the cutting edge of technology
Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools
In Return:
We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding!