This role is for a Principal DFT Engineer with 12 + years of proven experience in Design for Test
Experience coding in Verilog RTL, and scripting language like TCL, and/or Perl
Proficient in Unix/Linux environments
Core DFT skills considered crucial for this position should include some of the following: Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug
Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools
“Nice To Have” Skills and Experience:
Familiarity with IEEE 1149, 1500, 1687
Familiarity with Synthesis and Static Timing Analysis
Working knowledge of Siemens DFT tools
Ability to work both collaboratively on a team and independently.
Innovative and a passion for progress
Hard-working and excellent time management skills with an ability to multi-task
In Return:
Opportunity to work with some of the greatest minds in the industry!